A multi-processor data processing system may be arranged as an on-chip network with nodes of various types, such as processors, accelerators, IO, and memory connected via an interconnect fabric. At a high level, there are three basic node types, request, home and slave. A Request Node (RN) is a node that generates protocol transactions, including reads and writes, to the interconnect. These nodes could be fully coherent processors or IO coherent devices. A Home Node (HN) is a node that receives protocol transactions from RNs. Each address in the system has a Home which acts as the Point-of-Coherency (PoC) and Point of Serialization (PoS) for requests to that address. In a typical implementation, Homes for a range of addresses are grouped together as a Home Node. Each of these Home Nodes may include a system level cache and/or a snoop filter to reduce redundant snoops.
A Slave Node (SN) is a node that receives and completes requests from the HNs. An SN could be used from peripheral or main memory.
Data from a shared data resources may be accessed by a number of different processors and copies of the data may be stored in a local cache for rapid access. A cache coherence protocol may be used to ensure that all copies are up to date. The protocol may involve the HN exchanging snoop messages with the RNs having copies of data being accessed.
The HN may serialize accesses to an address on a first-come, first-served basis. For example, access to a designated device and resources of the HN may be reserved until a current transaction has been completed. A disadvantage of this approach is that HN resources may be reserved for longer than necessary, which may adversely affect system performance.